HYB25L256160AC Datasheet, PDF (4/55 Pages) Infineon Technologies AG – 256-Mbit Mobile-RAM

256-Mbit Mobile-RAM
Mobile-RAM
HYB25L256160AC
1
Overview
1.1
Features
• 16 Mbits × 16 organisation
• Fully synchronous to positive clock edge
• Four internal banks for concurrent operation
• Data mask (DM) for byte control with write and read data
• Programmable CAS latency: 2 or 3
• Programmable burst length: 1, 2, 4, 8, or full page
• Programmable wrap sequence: sequential or interleaved
• Random column address every clock cycle (1-N rule)
• Deep power down mode
• Extended mode register for Mobile-RAM features
• Temperature compensated self refresh with on-die temperature sensor
• Partial array self refresh
• Power down and clock suspend mode
• Automatic and controlled precharge command
• Auto refresh mode (CBR)
• 8192 refresh cycles / 64 ms
• Self-refresh with programmble refresh period
• Programmable power reduction feature by partial array activation during self-refresh
• V_DDQ = 1.8V or 2.5 V
• V_DD = 2.5 V
• P-TFBGA-54 package 9-by-6-ball array with 3 depopulated rows (12 x 8 mm²)
• Operating temperature range: commerical (0 °C to 70 °C)
Table 1 Performance ¹⁾
Part Number Speed Code
–7.5
–8
max. Clock Frequency
@CL3
f_CK3
133
125
min. Clock Period
@CL3
t_CK3
7.5
8.0
min. Access Time from Clock
@CL3
t_AC3
6.0
6.0
min. Clock Period
@CL2
t_CK2
9.5
9.5
min. Access Time from Clock
@CL2
t_AC2
6.0
6.0
1) for VDDQ = 2.5 V; see Table 10 for VDDQ dependent performance
Unit
MHz
ns
ns
ns
ns
1.2
Description
The 256-Mbit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as
4 banks x 4 Mbit x 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves
high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes
the output data to a system clock.
The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory
array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps
which drastically reduces the self refresh current, depending on the case temperature of the components in the
system application. In addition a “Deep Power Down Mode” is available. Operating the four memory banks in an
Data Sheet
4
V1.1, 2003-04-16