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HYB25L256160AC Datasheet, PDF (21/55 Pages) Infineon Technologies AG – 256-Mbit Mobile-RAM
HYB25L256160AC
256-Mbit Mobile-RAM
Electrical Characteristics
Table 9 Input and Output Capacitances
Parameter
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ
Symbol
CI1
CI2
CIO
Values
min. typ. max.
–
– 3.5
–
– 3.8
4.0 – 5.0
Unit
pF
pF
pF
Note/
Test Condition
1)
1)
1)
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 1 MHz,
TCASE = 25 ° C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
4.2
Timing Characteristics
Table 10 AC Timing Characteristics1)2)
Parameter
Symbol
–8
–7.5
Unit Note/ Test Condition
min. max. min. max.
Clock
DQ output access time from CLK
CK high-level width
CK low-level width
Clock cycle time
Clock frequency
Transition time
Setup and Hold Times
tAC3
–
7.5
–
7.5
ns VDDQ < 2.3 V 3)4)5)8)
–6
–6
ns VDDQ ≥ 2.3 V 3)4)5)8)
tAC2
–
7.5
–
7.5
ns VDDQ < 2.3 V 3)4)5)8)
–6
–6
ns VDDQ ≥ 2.3 V 3)4)5)8)
tCH
3–
2.5 –
ns –
tCL
3–
2.5 –
ns –
tCK3
8
–
7.5 –
ns VDDQ ≥ 2.3 V 3)
8–
8–
ns VDDQ < 2.3 V 3)
tCK2
9.5 –
9.5 –
ns 3)
fCK3
–
125 –
133
MHz VDDQ ≥ 2.3 V 3)
–
125 –
125
MHz VDDQ < 2.3 V 3)
fCK2
–
105 –
105
MHz 3)
tT
0.5 1.5
0.3 1.2
ns –
Input setup time
Input hold time
CKE setup time
CKE hold time
Mode register setup time
Power down moder entry time
Common Parameters
tIS
2–
tIH
1–
tCKS
2
–
tCKH
1
–
tRSC
2
–
tSB
08
1.5 –
0.8 –
1.5 –
0.8 –
2–
0 7.5
ns 6)
ns 6)
ns 6)
ns 6)
tCK –
ns –
Active to Read or Write delay
tRCD
Precharge command period
tRP
Active to Precharge command
tRAS
Active bank A to Active bank A period tRC
Active bank A to Active bank B delay tRRD
CAS to CAS command delay
tCCD
19 –
19 –
ns 7)
19 –
19 –
ns 7)
48 100000 45 100000 ns 7)
70 –
67 –
ns 7)
16 –
15 –
ns 7)
1–
1–
tCK –
Data Sheet
21
V1.1, 2003-04-16