PEB3264FV1.4 Datasheet, PDF (349/374 Pages) Infineon Technologies AG – Dual Channel Subscriber Line Interface Concept

DuSLIC
6.4.5 IOM-2 Interface Timing
Electrical Characteristics
6.4.5.1 Single-Clocking Mode
t _DCL
t _DCLh
DCL ^50%
FSC
t _{FSC_H2 tFSC_S t FSC_H1}
t _{DD_S} t _{DD_H}
t _FSC
DD
t _{dDU_low}
t _{dDU_high}
DU
Figure 88
IOM-2 Interface Timing – Single-Clocking Mode
ezm22016
Parameter
Symbol
Limit Values
min.
typ.
max.
Period DCL¹⁾ t_DCL
DCL high time t_DCLh
Period FSC¹⁾ t_FSC
FSC setup time t_{FSC_s}
FSC hold time 1 t_{FSC_h1}
FSC hold time 2 t_{FSC_h2}
DD setup time t_{DD_s}
DD hold time t_{DD_h}
DU low time²⁾
t_{dDU_low}
DU high time^{2) tdDU_high}
–
1/2048 –
0.4 × t_DCL 0.5 × t_DCL 0.6 × t_DCL
–
125
–
10
50
–
40
50
t_FSC – t_DCL – t_{FSC_s}
40
50
–
10
50
–
10
50
–
25
–
25
–
t_{dDU_low (min)} +
0.4[ns/pF] × C_Load[pF]
t_{dDU_high (min)} +
2 × R_pull-up[kΩ] × C_Load[pF]
1) The DCL frequency must be an integer multiple of the FSC frequency.
Unit
ms
µs
µs
ns
ns
ns
ns
ns
ns
ns
Preliminary Data Sheet
349
DS3, 2003-07-11