PEB3264FV1.4 Datasheet, PDF (154/374 Pages) Infineon Technologies AG – Dual Channel Subscriber Line Interface Concept

DuSLIC
08_H INTREG2 Interrupt Register 2 (read-only)
20_H
Y
Bit
7
6
5
4
3
2
1
0
LM- READY RSTAT LM-OK
THRES
IO[4:1]-DU
After a hardware reset, the RSTAT bit is set and generates an interrupt. Therefore the
default value of INTREG2 is 20_H. After reading all four interrupt registers, the INTREG2
value changes to 4F_H.
LM-THRES
Indication whether the level metering result is above or below the
threshold set by the CRAM coefficients
LM-THRES = 0 Level metering result is below threshold.
LM-THRES = 1 Level metering result is above threshold.
READY
Indication whether the ramp generator has finished. An interrupt is only
generated if the READY bit changes from 0 to 1. Upon a new start of the
ramp generator, the bit is set to 0. For further information regarding soft
reversal see Chapter 2.7.2.1.
READY = 0 Ramp generator active.
READY = 1 Ramp generator not active.
RSTAT
Hardware reset status since last interrupt.
RSTAT = 0 No hardware reset has occurred since the last interrupt.
RSTAT = 1 Hardware reset has occurred since the last interrupt.
LM-OK
Level metering sequence has finished. An interrupt is only generated if
the LM-OK bit changes from 0 to 1.
LM-OK = 0
Level metering result not ready.
LM-OK = 1
Level metering result ready.
IO[4:1]-DU Data on I/O pins 1 to 4 filtered by DUP-IO counter and interrupt generation
masked by the IO[4:1]-DU-M bits. A change of any of this bits generates
an interrupt.
Preliminary Data Sheet
154
DS3, 2003-07-11