1ED020I12-FT Datasheet, PDF (31/32 Pages) Infineon Technologies AG – 1ED020I12-FT

8
Application Notes
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1ED020I12-FT
Application NotesReference Layout for Thermal Data
8.1
Reference Layout for Thermal Data
The PCB layout shown in Figure 17 represents the reference layout used for the thermal characterisation. Pins 9
and 16 (GND1) and pins 1 and 8 (VEE2) require ground plane connections for achiving maximum power
dissipation. The 1ED020I12-FT is conceived to dissipate most of the heat generated through this pins.
Top Layer
Bottom Layer
Figure 17 Reference Layout for Thermal Data (Copper thickness 102 μm)
8.2
Printed Circuit Board Guidelines
Following factors should be taken into account for an optimum PCB layout.
• Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.
• The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained
to increase the effective isolation and reduce parasitic coupling.
• In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept
as short as possible.
• Lowest trace length for VEE2 to GND2 decoupling could be achieved with capacitor closed to pins 1 and 3.
Final Data Sheet
31
Rev 2.0, 2012-07-31