1ED020I12-FT Datasheet, PDF (15/32 Pages) Infineon Technologies AG – 1ED020I12-FT

EiceDRIVER™
1ED020I12-FT
Functional DescriptionNon-Inverting and Inverting Inputs
4.4
Non-Inverting and Inverting Inputs
There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output while
IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high, refer to Figure 7. A
minimum input pulse width is defined to filter occasional glitches.
4.5
Driver Output
The output driver section uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight control
of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is stable. Due to
the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by the gate resistor.
Furthermore, it reduces the power to be dissipated by the driver.
4.6
Two-Level Turn-Off
The Two-Level Turn-OFF introduces a second turn off voltage level at the driver output in between ON- and OFF-
level, refer to Figure 8. This additional level ensures lower V_CE overshoots at turn off by reducing gate emitter
voltage of the IGBT at short circuits or over current events. The V_GE level is adjusting the current of the IGBT at
the end two level turn off interval, the required timing is depending on stray inductance and over current at
beginning of two level turn off interval.
Reference voltage level and hold up time could be adjusted at TLSET pin. The reference voltage is set by the
required Zener diode connected between pin TLSET and GND2. The holdup time is set by the capacitor connected
to the same pin TLSET and GND2.
The hold time can be adjusted during switch on using the whole capacitance connected at pin TLSET including
capacitor, parasitic wiring capacitance and junction capacitance of Zener diode. When a switch on signal is given
the IC starts to discharge C_TLSET. Discharging C_TLSET is stopped after 500 ns. Then Ctlset is charged with an
internal charge current I_TLSET. When the voltage of the capacitor C_TLSET exceeds 7 V a second current source starts
charging C_TLSET up to V_ZDIODE. At the end of this discharge-charge cycle the gate driver is switched on.
The time between IN initiated switch-on signal (minus an internal propagation delay of approximately 200 ns) and
switch-on of the gate drive is sampled and stored digitally. It represents the two level turn off set time T_TLSET during
switch-off. Due to digitalization the tpdon time can vary in time steps of 50 ns.
If switch off is initiated from IN+, IN- or /RST signal, the gate driver is switched off immediately after internal
propagation delay of approximately 200 ns and V_OUT begins to decrease to the second gate voltage level.
For switch off initiated by DESAT, the gate driver switch off is delayed by desaturation sense to OUT delay,
afterwards V_OUT begins to decrease to the second gate voltage level.
For reaching second gate voltage level the output voltage V_OUT is sensed and compared with the Zener voltage
V_ZDIODE. When V_OUT falls below the reference voltage V_ZDIODE of the Zener diode the switch off process is
interrupted and V_OUT is adjusted to V_ZDIODE. OUT is switched to VEE2 after the holdup time has passed.
The Two-Level Turn-OFF function cannot be disabled.
Final Data Sheet
15
Rev 2.0, 2012-07-31