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XC167CI_02 Datasheet, PDF (30/79 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary | |||
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XC167
Derivatives
Preliminary
Functional Description
Table 4
XC167 Interrupt Nodes (contâd)
Source of Interrupt or PEC
Service Request
Control
Register
Vector
Location1)
Trap
Number
End of PEC Subch.
EOPIC
xxâ0130H
4CH / 76D
CAPCOM6 Timer T12
CCU6_T12IC xxâ0134H
4DH / 77D
CAPCOM6 Timer T13
CCU6_T13IC xxâ0138H
4EH / 78D
CAPCOM6 Emergency
CCU6_EIC
xxâ013CH
4FH / 79D
CAPCOM6
CCU6_IC
xxâ0140H
50H / 80D
SSC1 Transmit
SSC1_TIC
xxâ0144H
51H / 81D
SSC1 Receive
SSC1_RIC
xxâ0148H
52H / 82D
SSC1 Error
SSC1_EIC
xxâ014CH
53H / 83D
CAN0
CAN_0IC
xxâ0150H
54H / 84D
CAN1
CAN_1IC
xxâ0154H
55H / 85D
CAN2
CAN_2IC
xxâ0158H
56H / 86D
CAN3
CAN_3IC
xxâ015CH
57H / 87D
CAN4
CAN_4IC
xxâ0164H
59H / 89D
CAN5
CAN_5IC
xxâ0168H
5AH / 90D
CAN6
CAN_6IC
xxâ016CH
5BH / 91D
CAN7
CAN_7IC
xxâ0170H
5CH / 92D
RTC
RTC_IC
xxâ0174H
5DH / 93D
Unassigned node
---
xxâ012CH
4BH / 75D
Unassigned node
---
xxâ00FCH
3FH / 63D
Unassigned node
---
xxâ0160H
58H / 88D
1) Register VECSEG defines the segment where the vector table is located to.
Bitfield VECSC in register CPUCON1 defines the distance between two adjacent vectors. This table
represents the default setting, with a distance of 4 (two words) between two vectors.
Data Sheet
26
V1.0, 2002-10
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