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XC167CI_02 Datasheet, PDF (23/79 Pages) Infineon Technologies AG – 16-Bi t Single-Chip Microcontroller Preliminary | |||
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XC167
Derivatives
Preliminary
Functional Description
so-called General Purpose Registers (GPRs).
The upper 256 bytes of the DPRAM are directly bitaddressable. When used by a GPR,
any location in the DPRAM is bitaddressable.
1024 bytes (2 Ã 512 bytes) of the address space are reserved for the Special Function
Register areas (SFR space and ESFR space). SFRs are wordwide registers which are
used for controlling and monitoring functions of the different on-chip units. Unused SFR
addresses are reserved for future members of the XC166 Family. Therefore, they should
either not be accessed, or written with zeros, to ensure upward compatibility.
In order to meet the needs of designs where more memory is required than is provided
on chip, up to 12 Mbytes (approximately, see Table 3) of external RAM and/or ROM can
be connected to the microcontroller. The External Bus Interface also provides access to
external peripherals.
Table 3
XC167 Memory Map1)
Address Area
Start Loc. End Loc. Area Size2) Notes
Flash register space FFâF000H FFâFFFFH
4 Kbytes 3)
Reserved (Acc. trap) F8â0000H FFâEFFFH <0.5 Mbytes Minus Flash regs
Reserved for PSRAM E0â0800H F7âFFFFH <1.5 Mbytes Minus PSRAM
Program SRAM
E0â0000H E0â07FFH
2 Kbytes Maximum
Reserved for pr. mem. C2â0000H DFâFFFFH < 2 Mbytes Minus Flash
Program Flash
C0â0000H C1âFFFFH 128 Kbytes
Reserved
BFâ0000H BFâFFFFH 64 Kbytes
External memory area 40â0000H BEâFFFFH < 8 Mbytes Minus res. seg.
External IO area4)
20â0800H 3FâFFFFH < 2 Mbytes Minus TwinCAN
TwinCAN registers
20â0000H 20â07FFH
2 Kbytes
External memory area 01â0000H 1FâFFFFH < 2 Mbytes Minus segment 0
Data RAMs and SFRs 00â8000H 00âFFFFH 32 Kbytes Partly used
External memory area 00â0000H 00â7FFFH 32 Kbytes
1) Accesses to the shaded areas generate external bus accesses.
2) The areas marked with â<â are slightly smaller than indicated, see column âNotesâ.
3) Not defined register locations return a trap code.
4) Several pipeline optimizations are not active within the external IO area. This is necessary to control external
peripherals properly.
Data Sheet
19
V1.0, 2002-10
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