TLE7237GS Datasheet, PDF (27/36 Pages) Infineon Technologies AG – 8 Channel High-Side and Low-Side Relay Switch

TLE7237GS
Serial Peripheral Interface (SPI)
CS Low to High transition:
• Command decoding is only done, when after the falling edge of CS exactly a multiple (1, 2, 3, …) of eight SCLK
signals have been detected. In case of faulty transmission, the transmission error flag (TER) is set and the
command is ignored.
• Data from shift register is transferred into the input matrix register.
SCLK - Serial Clock: This input pin clocks the internal shift register. The serial input (SI) transfers data into the
shift register on the falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising
edge of the serial clock. It is essential that the SCLK pin is in low state whenever chip select CS makes any
transition.
SI - Serial Input: Serial input data bits are shifted in at this pin, the most significant bit first. SI information is read
on the falling edge of SCLK. The 8 bit input data consist of two parts (control and data). Please refer to Section 9.3
for further information.
SO Serial Output: Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state
until the CS pin goes to low state. New data will appear at the SO pin following the rising edge of SCLK. Please
refer to Section 9.3 for further information.
9.2
Daisy Chain Capability
The SPI of TLE7237GS provides daisy chain capability. In this configuration several devices are activated by the
same CS signal MCS. The SI line of one device is connected with the SO line of another device (see Figure 10),
which builds a chain. The ends of the chain are connected with the output and input of the master device, MO and
MI respectively. The master device provides the master clock MCLK, which is connected to the SCLK line of each
device in the chain.
device 1
device 2
device 3
SI
SO SI
SO SI
SO
MO
SPI
SPI
SPI
MI
MCS
MCLK
SPI_DasyChain.emf
Figure 10 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where one bit from SI line is shifted in each SCLK. The
bit shifted out can be seen at SO. After 8 SCLK cycles, the data transfer for one device has been finished. In single
chip configuration, the CS line must go high to make the device accept the transferred data. In daisy chain
configuration the data shifted out at device #1 has been shifted in to device #2. When using three devices in daisy
chain, three times 8 bits have to be shifted through the devices. After that, the MCS line must go high (see
Figure 11).
Data Sheet
27
Rev. 1.0, 2008-10-30