TLE7826G Datasheet, PDF (26/53 Pages) Infineon Technologies AG – Integrated double low-side switch, high-side/LED driver, hall supply, wake-up inputs and LIN communication with embedded MCU (32kB Flash)

TLE7826G
Reset Behavior and Window Watchdog
9
Reset Behavior and Window Watchdog
The SBC provides three different resets:
• V_INT-UV: reset of SBC upon undervoltage detection at internal supply voltage
• V_CC-UV: reset of SBC upon undervoltage detection at supply voltage (V_CC)
• Watchdog: reset of SBC caused by integrated window watchdog
Should the internal supply voltage become lower than the internal threshold the V_INT-Fail SPI bit will be reset in
order to indicate the undervoltage condition (V_INT-UV). All other SPI settings are also reset by this condition. The
V_INT-Fail feature can also be used to give an indication that the system supply was disconnected and therefore a
pre-setting routine of the microcontroller has to be started.
When the V_CC voltage falls below the reset threshold voltage V_RTx for a time duration longer than the filter time t_RR
the reset output is switched LOW and will be released after a programmable delay time (default setting for Power-
On-Reset) when V_CC > V_RTx. This is necessary for a defined start of the microcontroller when the application is
switched on after Power-On-Reset. As soon as an undervoltage condition of the output voltage (V_CC < V_RTx)
appears, the reset output is switched LOW again (V_CC-UV). The reset delay time can be shortened via SPI bit.
Please refer to Figure 17.
Table 11 Reset Behavior SBC
Affected by Reset
Reset Pin
V_INT-UV
“low”
Watchdog Timer
long open window
Operating Mode
SBC Standby
LS-Switches
“off”
Supply Output
“off”
HS-LED
“off”
Configuration Settings
Reset (“all bits cleared”)
V_CC-UV or Watchdog-Reset
“low”
long open window
SBC Standby
“off”
“off”
“off”
see Figure 10 “16-Bit SPI Input Data / Control
Word” on Page 20
After the above described delayed reset (LOW to HIGH transition at RESET pin) the window watchdog circuit is
started by opening a long open window in SBC Standby Mode. The long open window allows the microcontroller
to run its initialization sequences and then to trigger the watchdog via the SPI. Within the long open window period
a watchdog trigger is detected as a write access to the “window watchdog period bit field” within the SPI control
word. The trigger is accepted when the CSN input becomes HIGH after the transmission of the SPI word.
A correct watchdog trigger results in starting the window watchdog by opening a closed window with a width of
50% of the selected window watchdog period. This period, selected via the SPI window watchdog timing bit field,
is programmable in a wide range. The closed window is followed by an open window with a width of 50% of the
selected period. The microcontroller has to service the watchdog by periodically writing to the window watchdog
timing bit field. This write access has to meet the open window. A correct watchdog service immediately results in
starting the next closed window.
Should the trigger signal not meet the open window a watchdog reset is generated by setting the reset output low.
Then the watchdog again starts by opening a long open window. In addition, a “window watchdog reset flag” is set
within the SPI to monitor a watchdog reset. For fail safe reasons the TLE7826G is automatically switched to SBC
Standby mode if a watchdog trigger failure occurs. This minimizes the power consumption in case of a permanent
faulty microcontroller. This “window watchdog reset flag” will be cleared by any access to the SPI.
When entering a low power mode the watchdog can be requested to be enabled via an SPI bit. In SBC Stop Mode
the watchdog is only turned off once the current consumption at V_CC falls below the “watchdog current threshold”.
Data Sheet
26
Rev. 3.01, 2008-04-15