TLE7184F3V Datasheet, PDF (25/36 Pages) Infineon Technologies AG – System IC for B6 motor drives

TLE7184F-3V
Description of Modes, Protection and Diagnostic Functions
In this mode all external MOSFETs are actively or passively switched off. An Error is set and is shown as long as
VDD is sufficient high. In this mode VDD and VREG is switched off. As soon as VDD voltage reaches the V_VDDsleep
level the IC goes into the Sleep Mode.
Deadlock Mode
This mode is intended to prevent the IC for long time toggling in Over Temperature if a short is present at the VDD
pin.
There are 3 ways to enter this mode:
1. The IC is in Error Mode and a VDD Under Voltage Shut Down occurs.
2. The IC is in Normal Mode and a VDD Under Voltage Shut Down occurs.
3. The IC is in VREG Shut Down Mode and a VDD Under Voltage Shut Down occurs.
In this mode VDD and VREG regulators are switched off. The gates of the external MOSFETs are passively
clamped.
The VDHS switch is deactivated.
The IC will not react to IFMA or INH signals. Even a Over Temperature Shut Down detection will have no influence.
The internal logic is supplied and prevents the IC from going into “Go-to-Sleep Mode”.
The only way to leave this state is that VS is lower than V_VSLO, means a VS Under Voltage Lockout occurs. In this
case the IC goes to Sleep Mode.
VREG Shut Down Mode
This mode is intended to prevent the IC from long time toggling in Over Temperature if a short is present at the
VREG pin.
There are 2 ways to enter this mode:
1. The IC is in the Error Mode and a VREG Under Voltage Shut-down occurs.
2. The IC is in the Normal Mode and a VREG Under Voltage Shut-down occurs.
In this mode VREG is switched off, but VDD is still present. The VDHS switch is still active and the PWM interface
(IFMA) is working.
The IC will not react to IFMA or INH signals.
In this situation the µC is still able to provide diagnostic information by the interface. It can prevent the IC from Go-
to-Sleep Mode and can avoid unintended toggling as long there is no Over Temperature Shut Down.
This state can be left by 2 ways:
1. The µC has to set RGS to low for a time longer than t_sleep. In this case the IC goes to Sleep Mode.
2. If a VDD Under Voltage Shut Down occurs the IC will go into the Deadlock Mode.
9.2
Protection and Diagnosis Functions
9.2.1 Over Temperature Shut Down (OTSD)
If the junction temperature is exceeding the Over Temperature shut down level an error signal is set. The driver
IC will pull down the gate-source voltage of all external MOSFETs, deactivate the VDD and VREG supply and go
directly into the Sleep Mode.
In the Sleep Mode the regular wake-up conditions will be used. Over Temperature cycling is possible and will lead
to accelerated aging of the IC.
In Deadlock Mode an Over Temperature Shut Down is ignored.
Datasheet
25
Rev.1.2, 2016-01-27