TLE8080EM Datasheet, PDF (24/39 Pages) Infineon Technologies AG – Engine Management IC for Small Engines

TLE8080EM
Serial Peripheral Interface (SPI)
8
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a 16 bit full duplex synchronous serial slave interface, which uses four lines: SI, SO, SCLK and CSN.
8.1
SPI Signal Description
CSN - Chip Select:
The system micro controller selects the IC by means of the CSN pin. Whenever the pin is in low state, data transfer
can take place. As long as CSN is in high state, all signals at the SCLK and SI pins are ignored and SO is forced
to high impedance.
CSN - High to Low Transition:
SO changes from high impedance to high or low state depending on the Status Flag (see Chapter 8.2).
CSN - Low to High Transition:
End of transmission, the validation check of the communication is done (number of bits and valid command) and
valid commands are executed.
SCLK - Serial Clock:
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts information out on the rising edge of the serial clock. It is essential
that the SCLK pin is in low state whenever chip select CSN makes any transition.
SI - Serial Input:
Serial input data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read on the falling
edge of SCLK. Please refer to Section 8.2 for further information.
SO - Serial Output:
Data is shifted out serially at this pin, the MSB first. SO is in high impedance until the CSN pin goes to low. The
output level before the first rising edge of SCLK depends on the status flag. New data will appear at the SO pin
following the rising edge of SCLK. Please refer to Section 8.2 for further information.
8.2
SPI Protocol
The principle of the SPI communication is shown in Figure 13. The message from the micro controller must be
sent MSB first. The data from the SO pin is sent MSB first. The TLE8080EM samples data from the SI pin on the
falling edge of SCLK and shifts data out of the SO pin on the rising edge of SCLK. Each access must be terminated
by a rising edge of CSN.
All SPI messages must be exactly 16-bits long, otherwise the SPI message is discarded.
There is a one message delay in the response to each message (i.e. the response for message N will be returned
during message N+1).
The SPI protocol of the TLE8080EM provides three registers. The control register, the diagnosis, and the status
register. The control register contains the set up bits for the VR sensor interface and the control bits of channels
2, 4 and 5. The diagnosis register contains the diagnosis bits of the five low side switches. The status register
contains the status bits of the five low side switches, the watchdog status bit, and the watchdog time out bit. After
power-on reset, all register bits are set to reset state (see Chapter 8.2.1).
Data Sheet
24
Rev. 1.1, 2012-10-19