TLE8080EM Datasheet, PDF (10/39 Pages) Infineon Technologies AG – Engine Management IC for Small Engines

TLE8080EM
5V Supply, Reset and Supervision
Vs
t
V_V5DD
< tRR
VRT
V NRO
t RD
V_{NRO_H}
t
tRR
t RD
tRR
V _{NRO_L}
t
Figure 4 Reset Timing Diagram
5.3
Watchdog Operation
The TLE8088EE integrates a watchdog function which monitors the correct SPI communication with the micro
controller. A watchdog disable pin ( WD_DIS ) with an internal pull down current source is implemented. With a
high level the watchdog function is disabled.
For enabled watchdog function after power-up reset delay time ( t_RD ), valid SPI communication from the micro
controller must occur within the watchdog period ( t_WP ) specified in the electrical characteristics. A restart of the
watchdog period is done with a low to high transition of the CSN pin of a valid transmission of a 16 bit message.
A reset is generated (NRO goes LOW) for the time ( t_WR ) if there is no restart during the watchdog period as shown
in Figure 5.
Status after watchdog overflow:
• all outputs are switched off
• SPI registers are not influenced
• Watchdog Time Out bit in SPI status register is set
• first answer to SPI communication is the content of the status register
Switching of Outputs and reset of Watchdog Time Out Bit after watchdog overflow:
• Outputs 1 and 3 will be switched on with an positive edge at IN1 respectively IN3
• Outputs 2, 4 and 5 will be switched on with a write command to CMD register
• the watchdog time out bit will be reset with the rising edge of CSN of the first read command of the status
register
Data Sheet
10
Rev. 1.1, 2012-10-19