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TLE4678 Datasheet, PDF (24/31 Pages) Infineon Technologies AG – Low Drop Out Linear Voltage Regulator 5 V Fixed Output Voltage | |||
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TLE4678
Watchdog Function
Watchdog Timing
Positive edges at the watchdog input pin âWIâ are expected within the watchdog trigger time frame tWI,tr, otherwise
a low signal at pin âWOâ is generated. If a watchdog low signal at pin âWOâ is generated, it remains low for tWD,lo.
All watchdog timings are defined by charging and discharging the capacitor CD at pin âDâ. Thus, the watchdog
timing can be programmed by selecting CD. For timing details see also Figure 12.
In case a watchdog trigger time period tWI,tr different from the value for CD = 100nF is required, the delay
capacitorâs value can be derived from the specified value given in Item 8.2.22:
CD = 100nF Ã tWI,tr / tWI,tr,100nF
(8)
The watchdog output low time tWD,lo and the watchdog period tWD,p then becomes:
tWD,lo = tWD,lo,100nF Ã CD / 100nF
(9)
tWD,p = tWI,tr + tWD,lo
(10)
The formula is valid for CD ⥠10nF. For precise timing calculations consider also the delay capacitorâs tolerance.
VWI
V W I,h i
V W I,lo
VD
VDW,hi
VDW,lo
VWO
No positive
VWI edge
dVWI/ dt
outside spec
1/ fWI
t W I,p
t
tWI,tr
TWI,p
t
t W D ,lo
t W D ,lo
V W O,low
Figure 12 Timing Diagram Watchdog
T i mi n g Di a g ra m_ W a t ch d o g .vsd
t
Datasheet
24
Rev. 1.1, 2009-08-27
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