FOA2322A Datasheet, PDF (24/37 Pages) Infineon Technologies AG – 3.2 Gbi t /s Laser Driver IC for Telecom and Datacom Applications

FOA2322A
Electrical Characteristics
2.8
Laser and V_CC Supervising Circuit
If there is a laser fault (optical power deviates ±1 dB) this signal is stored and indicated
by LF (logic high). The fault indication (LF) can be reset with low level at RSTN or with
high level at RST or with power down (V_CC < V_CC Reset Threshold) only. After power up,
LF will always be cleared. Disabling the laser by LEN does not influence a previous fault
indication by LF. The laser fault generation can be switched off by connecting CFDEL to
V_CC. During RSTN is logic low or RST is logic high the circuit is in Reset state.
In case of changing RST = H or RSTN = L after laser fault recognition LF = H (after
t_FDEL) there is an additional delay time implemented which has the same value as the
Power On Delay.
If the supply voltage is lower than the V_CC reset threshold the indicator Hardware Alarm
(HWA) is still at the low level and the circuit is in Reset state.
During Power On Delay the circuit is in Reset state too. The Power On Delay is defined
as the delay after V_CC voltage has risen above the V_CC reset threshold. This time can be
adjusted by an external capacitor at COSC (Mode 1). The Reset N-Output of the
MAX 809S Power Supervisor IC can be connected to RSTN to use the reset function of
the MAX 809S.
The laser control by RST and RSTN is fully redundant. This means only an AND
combination of RST = 0 / RSTN = 1 can switch the laser on. The OR combination of
RST = 1 / RSTN = 0 switches the laser off (see Table 4 for clarification).
Table 4
Laser Diode Currents Enable / Disable Signals
RST
X
LEN
1
RSTN
X
In Case of V_CC < Reset LDOFF Modulation Bias
LF (high
Laser Fault Threshold V_CC
Enable¹⁾ Enable¹⁾ active)
0
X
1
0
0
0
1 XX
X
X
1
0
0
0
XX0
X
X
1
0
0
0
XXX
X
yes
001
1
no²⁾
001
0
no²⁾
1
0
1³⁾
0
0⁴⁾
1
0
0
0
1³⁾
1
0
1) _{Internal signal}
2) _{After Power On Delay}
3) _{After tFDEL}
4) _{Sink current enabled = Low}
Table 4 shows the static states of these signals. Dynamic changes or delays due to
external delay capacitors are not shown.
Preliminary Data Sheet
20
2001-05