TLE7233G_15 Datasheet, PDF (23/33 Pages) Infineon Technologies AG – 4 channel low-side driver with limp home

SPI Driver for Enhanced Relay Control
SPIDER - TLE7233G
Serial Peripheral Interface (SPI)
9
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred. The interface provides daisy chain capability.
SO
SI
CS
SCLK
time
CS MSB 6
5
MSB 6
5
4
3
4
3
2
1
LSB
2
1 LSB
SPI.emf
Figure 10 Serial Peripheral Interface
The SPI protocol is described in Chapter 9.3. It is reset to the default values after power-on reset.
9.1
SPI Signal Description
CS - Chip Select:
The system micro controller selects the TLE7233G by means of the CS pin. Whenever the pin is in low state, data
transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored and SO is
forced into a high impedance state.
CS High to Low transition:
• The diagnosis information is transferred into the shift register.
• SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. The transmission error flag is set after any kind of reset, so a reset
between two SPI commands is indicated. For details, please refer to Figure 11. This information stays
available to the first rising edge of SCLK.
Datasheet
23
Rev. 1.2, 2014-05-09