HYS64D64020HBDL Datasheet, PDF (21/27 Pages) Infineon Technologies AG – 200-Pin Small Outline Dual-In-Line Memory Modules

HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
SPD Contents
4
SPD Contents
Table 14 SPD Codes for HYS64D64020HBDL–5–C and HYS64D64020GBDL–5–C
Product Type
HYS64D64020GBDL–5–C HYS64D64020HBDL–5–C
Organization
512 MB
512 MB
×64
×64
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC3200S–3033–1
JEDEC SPD Revision
Rev 1.0
Rev 1.0
Byte# Description
HEX
HEX
0
Programmed SPD Bytes in E2PROM 80
80
1
Total number of Bytes in E2PROM
08
08
2
Memory Type (DDR = 07h)
07
07
3
Number of Row Addresses
0D
0D
4
Number of Column Addresses
0A
0A
5
Number of DIMM Ranks
02
02
6
Data Width (LSB)
40
40
7
Data Width (MSB)
00
00
8
Interface Voltage Levels
04
04
9
t_CK @ CL_max (Byte 18) [ns]
50
50
10
t_AC SDRAM @ CL_max (Byte 18) [ns]
50
50
11
Error Correction Support
00
00
12
Refresh Rate
82
82
13
Primary SDRAM Width
08
08
14
Error Checking SDRAM Width
00
00
15
t_CCD [cycles]
01
01
16
Burst Length Supported
0E
0E
17
Number of Banks on SDRAM Device 04
04
18
CAS Latency
1C
1C
19
CS Latency
01
01
20
Write Latency
02
02
21
DIMM Attributes
20
20
22
Component Attributes
C1
C1
23
t_CK @ CL_max -0.5 (Byte 18) [ns]
60
60
24
t_AC SDRAM @ CL_max -0.5 [ns]
50
50
25
t_CK @ CL_max -1 (Byte 18) [ns]
75
75
26
t_AC SDRAM @ CL_max -1 [ns]
50
50
27
t_RPmin [ns]
3C
3C
28
t_RRDmin [ns]
28
28
29
t_RCDmin [ns]
3C
3C
30
t_RASmin [ns]
28
28
31
Module Density per Rank
40
40
32
t_AS, t_CS [ns]
60
60
Data Sheet
21
Rev. 1.1, 2004-05