TLE4470_08 Datasheet, PDF (2/24 Pages) Infineon Technologies AG – Dual Low-Drop Voltage Regulator Very low dropout

TLE 4470
use of an external voltage divider the main output voltage can be set to V_Q2 ≥ 5 V for the
TLE 4470 G type (PG-DSO-20 package). V_Q1 is compared to the voltage at pin ADJ2,
which is proportional to the output voltage V_Q2. A control amplifier drives the base of the
series PNP transistor via a buffer.
The main output voltage V_Q2 is tracked to the accuracy of the stand-by output.
For the TLE 4470 GS (PG-DSO-14 package) the output voltage is fixed to 5 V.
To save energy e.g. in battery powered body electronic applications, the main regulator
can be switched off via the disable input, which causes the current consumption to drop
to 180 µA typical.
Two additional features of the TLE 4470 are an early warning comparator (can be used
e.g. to monitor the supply voltage V_I) and reset generator with an adjustable reset delay
time. The TLE 4470 G (PG-DSO-20 package) has in addition an adjustable reset
switching threshold. This feature is useful with microprocessors which guarantee a safe
operation down to voltages below the internally set reset threshold of 4.65 V typical.
Two functions are included in the reset generator, a power-on-reset and an under-
voltage reset. The power-on-reset feature is necessary for a defined start of the
microprocessor when switching on the application. The reset signal is kept low for a
certain delay time after the output voltage V_Q1 of the regulator has surpassed the reset
threshold. An external delay capacitor sets this delay time. The under voltage reset
circuit supervises the stand-by output voltage. In case V_Q1 falls below the reset switching
threshold the reset output is set LOW after a short reaction time. The reset LOW signal
is generated down to an output voltage V_Q1 of 1 V.
PG-DSO-14
D1
DIS 2
GND 3
GND 4
GND 5
RQ 6
SQ 7
14 SI
13 Ι
12 GND
11 GND
10 GND
9 Q2
8 Q1
AEP02152
PG-DSO-20
RADJ 1
D2
DIS 3
GND 4
GND 5
GND 6
GND 7
RQ 8
SQ 9
Q1 10
20 SI
19 Ι 1
18 Ι 2
17 GND
16 GND
15 GND
14 GND
13 Q2
12 Q2
11 ADJ2
AEP02151
Figure 1 Pin Configuration (top view)
Data Sheet
2
Rev. 1.2, 2008-03-20