TLE4470_08 Datasheet, PDF (14/24 Pages) Infineon Technologies AG – Dual Low-Drop Voltage Regulator Very low dropout

TLE 4470
Input, Output
The input capacitor C_I is necessary for compensating line influences. Using a resistor of
approx. 1 Ω in series with C_I, the LC circuit of input inductivity and input capacitance can
be damped. To stabilize the regulation circuits of the stand-by and main regulator, output
capacitors C_Q1 and C_Q2 are necessary. Stability is guaranteed at values C_Q1 ≥ 6 µF and
C_Q2 ≥ 10 µF, both with an ESR ≤ 10 Ω within the operating temperature range.
For the TLE 4470 G (PG-DSO-20) the output voltage V_Q2 of the main regulator can be
adjusted to 5 V ≤ V_Q2,nom ≤ 20 V by connecting an external voltage divider to the voltage
adjust pin ADJ2. For V_Q2 = 5 V the voltage adjust pin has to be connected directly to the
main output.
For calculating V_Q2 or R₁ and R₂ respectively the following equations can be used:
V_Q2 = V_Q1 × (1 + R₁ / R₂)
(1)
or
R₁ = R₂ × (V_Q2 / V_Q1 - 1)
(2)
Disable
The main regulator of the TLE 4470 can be switched OFF by a voltage above 2.3 V at
pin DIS. Reducing this voltage below 1.4 V will switch ON the main regulator again.
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C_D which can be calculated as follows:
C_D = (∆t × I_D,c) / ∆V
(3)
Definitions:
• C_D = delay capacitor
• ∆t = reset delay time
• I_D,c = charge current, typical 5 µA
• ∆V = V_DU, typical 1.8 V
• V_DU = upper delay switching threshold at C_D for reset delay time
The reset reaction time t_rr is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 2 µs
for delay capacitor of 100 nF. For other values for C_D the reaction time can be estimated
using the following equation:
t_rr ≈ 20 s/F × C_D
(4)
Data Sheet
14
Rev. 1.2, 2008-03-20