TLE7240SL Datasheet, PDF (19/28 Pages) Infineon Technologies AG – 8 Channel Protected Low-Side Relay Switch

SPI Driver for Enhanced Relay Control
SPIDER - TLE 7240SL
Serial Peripheral Interface (SPI)
8
Serial Peripheral Interface (SPI)
The diagnosis and control interface is based on a serial peripheral interface (SPI).
The SPI is a full duplex synchronous serial slave interface, which uses four lines: SO, SI, SCLK and CS. Data is
transferred by the lines SI and SO at the data rate given by SCLK. The falling edge of CS indicates the beginning
of a data access. Data is sampled in on line SI at the falling edge of SCLK and shifted out on line SO at the rising
edge of SCLK. Each access must be terminated by a rising edge of CS. A modulo 8 counter ensures that data is
taken only, when a multiple of 8 bit has been transferred, while the minimum of 16 bit is also taken into
consideration. Therefore the interface provides daisy chain capability even with 8 bit SPI devices.
SO
SI
MSB 14 13 12 11 10 9 8
7
65
43
2
1
LSB
MSB 14 13 12 11 10 9 8
7
65
43
2
1 LSB
CS
SCLK
time
SPI. emf
Figure 8 Serial peripheral interface
The SPI protocol is described in Section 8.3. It is reset to the default values after power-on reset.
8.1
SPI Signal Description
CS - Chip Select:
The system micro controller selects the SPIDER - TLE 7240SL by means of the CS pin. Whenever the pin is in
low state, data transfer can take place. When CS is in high state, any signals at the SCLK and SI pins are ignored
and SO is forced into a high impedance state.
CS High to Low transition:
• The diagnosis information is transferred into the shift register.
• SO changes from high impedance state to high or low state depending on the logic OR combination between
the transmission error flag (TER) and the signal level at pin SI. As a result, even in daisy chain configuration,
a high signal indicates a faulty transmission. The transmission error flag is set after any kind of reset, so a reset
between two SPI commands is indicated. For details, please refer to Figure 9. This information stays available
to the first rising edge of SCLK.
TER
SI
OR
1
SO
0
SI SPI ^SO
S
CS
SCLK
S
Figure 9 Transmission Error Flag on SO Line
TER.emf
Data Sheet
19
Rev. 1.1, 2009-04-15