TLE7209-2R_07 Datasheet, PDF (16/32 Pages) Infineon Technologies AG – 7 A H-Bridge for DC-Motor Applications

TLE 7209-2R
Circuit Description
Table 10 Encoding of the Diagnostic Bits of OUT1 and OUT2
DIA21 DIA20 DIA11 DIA10 Description
latch
behavior
1
1
0
0
Short circuit over load (SCOL)
latched
-
-
0
1
Short circuit to battery on OUT1 (SCB1) latched
-
-
1
0
Short circuit to ground on OUT1 (SCG1) latched
-
-
1
1
No error detected on OUT1
-
0
0
1
1
Open load (OL)
latched
0
1
-
-
Short circuit to battery on OUT2 (SCB2) latched
1
0
-
-
Short circuit to ground on OUT2 (SCG2) latched
1
1
-
-
No error detected on OUT2
-
0
0
0
0
Under Voltage on Pin Vs
not latched
Failure Encoding in case of multiple faults
If multiple faults are stored in the failure register, the faults that are encoded in the DIAxx
bits can not be displayed simultaneously due to the encoding scheme that is used. In this
case, errors are encoded according to the following priority list.
– Priority 1: Under Voltage (please note that after removal of Under Voltage, the original
error will be restored, see below)
– Priority 2: Short circuit across the load
– Priority 3: all other short circuits
– Priority 4: open load
If a failure of higher priority is detected, the failures of lower priority are no longer visible
in the encoded SPI message.
Fault storage and reset of the Diagnosis Register DIA_REG
Register DIA_REG is reset upon the following conditions:
– With the rising edge of the CSN-Signal after the SPI-instruction RD_DIA. This reset
only takes place if the correct number of 16 SCK pulses has been counted.
– When the voltage on DMS exceeds the threshold for detecting SPI-Mode (after Under
Voltage condition). Under Voltage on Vs (typ. < 5,0V) sets Bit 0.... Bit 3 of DIA_REG
to 0000. If Vs rises above the Under Voltage level, Bits of DIA_REG are restored
(when DMS > 3.5V).
– A rising edge on EN while DIS=0 or a falling edge on DIS while EN=1 re-activates the
output power-stages, and resets the DIA_REG register.
Data Sheet
16
Rev. 1.4, 2007-04-05