TLE7209-2R_07 Datasheet, PDF (10/32 Pages) Infineon Technologies AG – 7 A H-Bridge for DC-Motor Applications

TLE 7209-2R
Circuit Description
The first two bits of an instruction may be used to establish an extended device-
addressing. This gives the opportunity to operate up to 4 Slave-devices sharing one
common CSN signal from the Master-Unit (see Figure 7)
DMS
CSN
SCK
SDI
SDO
D IS
EN
s h ift-re g is te r
OR
8
D IA _ R E G
R eset
S P I pow er-
s u p p ly
S P I-C o n tro l:
-> s ta te m a c h in e
-> c lo c k c o u n te r
-> in s tru c tio n re c o g n itio n
8
D ia g n o s tic s
DMS
U nd er-
v o lta g e
Figure 6 SPI block-diagram
2.4.2.2 Characteristics of the SPI Interface
1. When DMS is > 3.5V, the SPI is active, independently of the state of EN or DIS. During
active reset conditions (DMS < 3.5V) the SPI is driven into its default state. When reset
becomes inactive, the state machine enters into a wait-state for the next instruction.
2. If the slave select signal at CSN is inactive (high), the state machine is forced to enter
the wait-state, i.e. the state machine waits for the following instruction.
3. During active (low) state of the select signal CSN the falling edge of the serial clock
signal SCK will be used to latch the input data at SDI. Output data at SDO are driven
with the rising edge of SCK (see timing diagram Figure 13)
4. Chip-address:
In order to establish the option of extended addressing the uppermost two bits of the
instruction-byte (i.e the first two SDI-bits of a Frame) are reserved to send a chip-
address. To avoid a bus conflict the output SDO must stay high impedance during the
addressing phase of a frame (i.e. until the address-bits are recognized as valid chip-
address). If the chip-address does not match, the data at SDI will be ignored and SDO
remains high impedance for the complete frame. See also Figure 7
5. Verification byte:
Simultaneously to the receipt of an SPI instruction TLE 7209-2R transmits a
verification byte via the output SDO to the controller. Refer to Figure 8. This byte
indicates normal or abnormal operation of the SPI. It contains an initial bit pattern and
a flag indicating an error occurred during the previous access.
Data Sheet
10
Rev. 1.4, 2007-04-05