ICE2QR0665G_14 Datasheet, PDF(13/27 Page) Infineon Technologies AG – Off-Line SMPS Quasi-Resonant PWM Controller with integrated 650V CoolMOS? and startup cell in DSO-16/12

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ICE2QR0665G_14 Datasheet, PDF (13/27 Pages) Infineon Technologies AG – Off-Line SMPS Quasi-Resonant PWM Controller with integrated 650V CoolMOS? and startup cell in DSO-16/12

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CoolSETâ¢Q1

ICE2QR0665G

Functional Description

A further comparator is implemented to detect dangerous current levels (VCSSW) which could occur if one or

more transformer windings are shorted or if the secondary diode is shorted. To avoid an accidental latch off, a

spike blanking time of tCSSW is integrated in the output path of the comparator.

3.4.1 Foldback Point Correction

When the main bus voltage increases, the switch on time becomes shorter and therefore the operating

frequency is also increased. As a result, for a constant primary current limit, the maximum possible output

power is increased which is beyond the converter design limit.

To avoid such a situation, the internal foldback point correction circuit varies the VCS voltage limit according to

the bus voltage. This means the VCS will be decreased when the bus voltage increases. To keep a constant

maximum input power of the converter, the required maximum VCS versus various input bus voltage can be

calculated, which is shown in Figure 7.

Figure 7 Variation of the VCS limit voltage according to the IZC current

According to the typical application circuit, when MOSFET is turned on, a negative voltage proportional to bus

voltage will be coupled to auxiliary winding. Inside CoolSETTM Q1, an internal circuit will clamp the voltage on

ZC pin to nearly 0V. As a result, the current flowing out from ZC pin can be calculated as

When this current is higher than IZC_FS, the amount of current exceeding this threshold is used to

generate an offset to decrease the maximum limit on VCS. Since the ideal curve shown in Figure 7 is a

nonlinear one, a digital block in CoolSETTM Q1 is implemented to get a better control of maximum

output power. Additional advantage to use digital circuit is the production tolerance is smaller

compared to analog solutions. The typical maximum limit on VCS versus the ZC current is shown in

Figure 8.

Data Sheet

V2.1, 2014-04-01

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