XC2797X Datasheet, PDF (124/147 Pages) Infineon Technologies AG – 16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

XC2797X
XC2000 Family Derivatives / High Line
Electrical Parameters
4.7.5 External Bus Timing
The following parameters specify the behavior of the XC2797X bus interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 30 Parameters
Parameter
Symbol
Values
Unit Note /
Min. Typ. Max.
Test Condition
CLKOUT Cycle Time¹⁾
t₅ CC −
1 / f_SYS −
ns
CLKOUT high time
t₆ CC 2
−
−
CLKOUT low time
t₇ CC 2
−
−
CLKOUT rise time
t₈ CC −
−
3
ns
CLKOUT fall time
t₉ CC −
−
3
1) The CLKOUT cycle time is influenced by PLL jitter. For longer periods the relative deviation decreases (see
PLL deviation formula).
t₅
t₆
t₇
t₉
t₈
CLKOUT
MC_X_ EBCCLKOUT
Figure 21 CLKOUT Signal Timing
Note: The term CLKOUT refers to the reference clock output signal which is generated
by selecting f_SYS as the source signal for the clock output signal EXTCLK on pin
P2.8 and by enabling the high-speed clock driver on this pin.
Data Sheet
124
V1.2, 2010-09