ICE3PCS02G Datasheet, PDF (11/20 Pages) Infineon Technologies AG – Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)

Ramp Profile
Ave(Iin) at ICOMP
CCM-PFC
ICE3PCS02G
Functional Description
immediately and maintained in off state for the current
PWM cycle. The signal T_OFFMIN resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 11.
Gate
Drive
t
Figure 9
Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 3
(ICOMP). The PWM cycles starts with the Gate turn off
for a duration of T_OFFMIN (600ns typ.) and the ramp is
kept discharged. The ramp is allowed to rise after the
T_OFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D_OFF.
Figure 10 shows the timing diagrams of the T_OFFMIN and
the gate waveforms.
Clock
V ⁽¹⁾
C,ref
Toff_min 600 ns
PWM Cycle
Toff _min
600ns
Peak current limit
Current
limit Latch
RQ
SQ
Current loop
PWM on signal
PWM on
Latch
RQ
SQ
High = turn on Gate
Figure 11
PWM LOGIC
3.8 System Protection
The IC provides numerous protection features in order
to ensure the PFC system in safe operation.
3.8.1 Peak Current Limit (PCL)
The IC provides a cycle by cycle peak current limitation
(PCL). It is active when the voltage at pin 1 (ISENSE)
reaches -0.4V. This voltage is amplified by a factor of -
2.5 and connected to comparator with a reference
voltage of 1.0V as shown in Figure 12. A deglitcher with
200ns after the comparator improves noise immunity to
the activation of this protection.
Vram p
GATE
Ramp
Released
t
V (1)
c,ref
is
a
function
of
V ICOMP
Figure 10
Ramp and PWM waveforms
Full-wave
rectifier
ISENSE
RCS
Rshunt
Iin
SGND
G=-2.5
AO2
200ns
PCL
C5
1V
3.7 PWM Logic
The PWM logic block prioritizes the control input signal
and generates the final logic signal to turn on the driver
stage. The speed of the logic gates in this block,
together with the width of the reset pulse T_OFFMIN, are
designed to meet a maximum duty cycle D_MAX of 95%
at the GATE output under 65kHz of operation.
In case of high input currents which results in Peak
Current Limitation, the GATE will be turned off
Figure 12 Peak Current Limit (PCL)
3.8.2 Open Loop Protection (OLP)
Whenever VSENSE voltage falls below 0.5V, or
equivalently V_OUT falls below 20% of its rated value, it
indicates an open loop condition (i.e. VSENSE pin not
connected) or an insufficient input voltage V_IN for
normal operation. It is implemented using comparator
Version 2.0
11
5 May 2010