ICE2PCS04 Datasheet, PDF (11/19 Pages) Infineon Technologies AG – Standalone PFC Controller in CCM with Input Brown-Out Protection

voltage at pin VCOMP. This block has been designed
to support the wide input voltage range (85-265VAC).
3.7 PWM Logic
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse T_OFFMIN,
are designed to meet a maximum duty cycle D_MAX of
95% at the GATE output.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 13.
CCM-PFC
ICE2PCS04/G
Functional Description
From
L1
Full-wave
Retifier _R7
D1
R3 ^Vout
C2
R4
Current Loop
+
PWM Generation
V_IN
Av(I_IN)
Nonlinear
Gain
t
Gate Driver
GATE
OTA1
3V
VSENSE
Peak Current
Limit
Current
Limit Latch
Q
S
L1
R
G1
HIGH =
turn GATE on
ICE2PCS04/G
VCOMP
R6
Current Loop
PWM on signal
Toffmin
385ns
PWM on
Latch
S _{L2 Q}
R
Figure 13 PWM Logic
3.8 Voltage Loop
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage V_OUT. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from V_OUT. The pin VSENSE is the input of
OTA1 which has an accurate internal reference of 3V
(±2%). Figure 14 shows the important blocks of this
voltage loop.
3.8.1 Voltage Loop Compensation
The compensation of the voltage loop is installed at the
VCOMP pin (see Figure 14). This is the output of OTA1
and the compensation must be connected at this pin to
ground. The compensation is also responsible for the
soft start function which controls an increasing AC input
current during start-up.
C4
C5
Figure 14 Voltage Loop
3.8.2 Enhanced Dynamic Response
Due to the low frequency bandwidth of the voltage loop,
the dynamic response is slow and in the range of about
several 10ms. This may cause additional stress to the
bus capacitor and the switching transistor of the PFC in
the event of heavy load changes.
The IC provides therefore a “window detector” for the
feedback voltage V_VSENSE at pin 6 (VSENSE).
Whenever V_VSENSE exceeds the reference value (3V)
by +5%, it will act on the nonlinear gain block which in
turn affect the gate drive duty cycle directly. This
change in duty cycle is bypassing the slow changing
VCOMP voltage, thus results in a fast dynamic
response of V_OUT.
3.9 Output Gate Driver
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 15) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (GATE) is typically
clamped at 15V.
Version 2.0
11
10 October 2007