ICE2PCS04 Datasheet, PDF (10/19 Pages) Infineon Technologies AG – Standalone PFC Controller in CCM with Input Brown-Out Protection

CCM-PFC
ICE2PCS04/G
Functional Description
3.6 Average Current Control
3.6.1 Complete Current Loop
The complete system current loop is shown in Figure
10.
From
Full-wave
Retifier
L1
R7
R2
R1
ISENSE
Current Loop
ICOMP
C3
Current Loop
Compensation
OTA2
1.0mS
+/-50uA (linear range)
S2
4.2V
Fault
ICE2PCS04/G
D1
R3 ^Vout
C2
R4
GATE
voltage
proportional to
averaged
Inductor current
PWM
Comparator
C1
Gate
Driver
RQ
S
PWM Logic
Nonlinear
Gain
Input From
Voltage Loop
Figure 10 Complete System Current Loop
It consists of the current loop block which averages the
voltage at pin ISENSE, resulted from the inductor
current flowing across R1. The averaged waveform is
compared with an internal ramp in the ramp generator
and PWM block. Once the ramp crosses the average
waveform, the comparator C1 turns on the driver stage
through the PWM logic block. The Nonlinear Gain block
defines the amplitude of the inductor current. The
following sections describe the functionality of each
individual blocks.
3.6.2 Current Loop Compensation
The compensation of the current loop is done at the
ICOMP pin. This is the OTA2 output and a capacitor C3
has to be installed at this node to ground (see Figure
10). Under normal mode of operation, this pin gives a
voltage which is proportional to the averaged inductor
current. This pin is internally shorted to 4.2V in the
event of standby mode.
3.6.3 Pulse Width Modulation (PWM)
The IC employs an average current control scheme in
continuous conduction mode (CCM) to achieve the
power factor correction.
Assuming the voltage loop is working and output
voltage is kept constant, the off duty cycle D_OFF for a
CCM PFC system is given as
D_OFF
=
---V----^I--^N----
V_OUT
From the above equation, D_OFF is proportional to V_IN.
The objective of the current loop is to regulate the
average inductor current such that it is proportional to
the off duty cycle D_OFF, and thus to the input voltage
V_IN. Figure 11 shows the scheme to achieve the
objective.
ramp profile
ave(I_IN) at ICOMP
GATE
drive
t
Figure 11 Average Current Control in CCM
The PWM is performed by the intersection of a ramp
signal with the averaged inductor current at pin 5
(ICOMP). The PWM cycle starts with the Gate turn off
for a duration of T_OFFMIN (400ns typ.) and the ramp is
kept discharged. The ramp is then allowed to rise after
T_OFFMIN expires. The off time of the boost transistor
ends at the intersection of the ramp signal and the
averaged current waveform. This results in the
proportional relationship between the average current
and the off duty cycle D_OFF.
Figure 12 shows the timing diagrams of T_OFFMIN and the
PWM waveforms.
T_OFFMIN
400ns
PWM cycle
V_CREF(1)
V_RAMP
PWM
ramp
released
t
(1) _{VCREF is a function of VICOMP}
Figure 12 Ramp and PWM waveforms
3.6.4 Nonlinear Gain Block
The nonlinear gain block controls the amplitude of the
regulated inductor current. The input of this block is the
Version 2.0
10
10 October 2007