TLE6232GP Datasheet, PDF (10/19 Pages) Infineon Technologies AG – Smart Six Channel Low-Side Switch

SPI Interface
Power Stages 1...6
SCON_REG
Data Sheet TLE 6232 GP
Power Stages 1...6
MUX_REG
CS
SCLK
CS
SCK
SI
SO
Shift Register
SPI Control:
State Machine
Clock Counter
Control Bits
Parity Generator
DIA_REG
Power Stages 1...6
SPI Communication
A SPI communication starts with a SPI instruction (SI control word) sent from the controller to
TLE 6232 GP. Simultaneously the device sends the first SO byte back to the µC.
During a writing cycle the controller sends the data after the SPI instruction, beginning with the
MSB. During a reading cycle, after having received the SPI instruction, TLE 6232 GP sends
the corresponding data to the controller, also starting with the MSB.
The SPI Interface consists of three register:
- MUX_REG: 8-bit (1 byte) length for parallel operation mode (IN1 ... IN6 enabled or not)
- SCON_REG: 8-bit (1 byte) length for serial control of the outputs (serial data bits)
V1.2
Page 10
08.Oct. 2003