TDA4916GG Datasheet, PDF (10/30 Pages) Siemens Semiconductor Group – SMPS-IC with MOSFET Driver Output

TDA 4916 GG
Reference Voltage V_REF
The reference voltage source makes available a source with a high-stability temperature
characteristic which can be used for external connection to the operational amplifier, the
fault comparators, the frequency generator, or to other external units. The voltage
source is short-circuit-proof to ground.
Synchronization I SYN, Q SYN
The device has an input and an output for synchronization. In the case of a synchronized
device (slave), its output Q SIP is in phase opposition to the output Q SIP of the
synchronizing device (master). In the case of an unconnected input I SYN, or with
connection to V_REF, or also when a series capacitor (without switching transitions) is
connected, the device receives its clock from the internal frequency generator in
accordance with the circuit connected to it. As soon as switching transitions appear at
I SYN, switchover to external synchronization and vice versa takes place after a delay.
After a switchover process, a few clock cycles must elapse in addition to the delay before
the frequency and phase achieve their steady states.
Series Feed SF
The Series Feed circuit section is used to turn-OFF the external series-feed transistor
when energy recovery commences. As a result there is minimum power loss in the
supply to the device. With the series-feed transistor turned-OFF, its drive current flows
via VS to V_S.
SIPMOS Driver Output Q SIP
The output is High active. The time during which the output is active can be continuously
varied.
The duration of the rising edge of the frequency generator signal is the minimum time
during which the output can be Low.
The duration of the falling edge of the frequency generator signal is the maximum time
during which the output can be High.
The output driver is designed as a push-pull stage. The output current is limited internally
to the specified values.
Output Q SIP is connected via diodes to the supply V_S QSIP and 0V QSIP.
A protection circuit SS lies between Q SIP and GND to clamp the output to ground at low
impedance in the event of undervoltage at V_S.
Version 2.0
10
1 May 1996