ICE3B0365L Datasheet, PDF(10/28 Page) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOS™ and Latched off Mode

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ICE3B0365L Datasheet, PDF (10/28 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/Depletion CoolMOS™ and Latched off Mode

◁

CoolSETâ¢-F3

ICE3xxx65L

Functional Description

3.5

Current Limiting

PWM Latch Latched Off

FF1

Mode

Spike

Blanking

190ns

Current Limiting

1.66V

C11

Propagation-Delay

Compensation

short winding in the transformer or the secondary diode

is shorten. To ensure that there is no accidentally

entering of the Latched Mode by the comparator C11 a

spike blanking with 190ns is integrated in the output

path of comparator C11.

3.5.1

Leading Edge Blanking

VSense

Vcsth

tLEB = 220ns

PWM-OP

&

G10

Active Burst

Mode

Vcsth

C10

Leading

Edge

Blanking

220ns

C12

0.257V

10k

1pF

D1

CS

t

Figure 10 Leading Edge Blanking

Each time when the internal CoolMOSâ¢ is switched

on, a leading edge spike is generated due to the

primary-side capacitances and secondary-side rectifier

reverse recovery time. This spike can cause the gate

drive to switch off unintentionally. To avoid a premature

termination of the switching pulse, this spike is blanked

out with a time constant of tLEB = 220ns. During this

time, the gate drive will not be switched off.

Figure 9 Current Limiting Block

There is a cycle by cycle Current Limiting realized by

the Current-Limit comparator C10 to provide an

overcurrent detection. The source current of the

internal CoolMOSâ¢ is sensed via an external sense

resistor RSense . By means of RSense the source current

is transformed to a sense voltage VSense which is fed

into the pin CS. If the voltage VSense exceeds the

internal threshold voltage Vcsth the comparator C10

immediately turns off the gate drive by resetting the

PWM Latch FF1. A Propagation Delay Compensation

is added to support the immediate shut down without

delay of the internal CoolMOSâ¢ in case of Current

Limiting. The influence of the AC input voltage on the

maximum output power can thereby be avoided.

To prevent the Current Limiting from distortions caused

by leading edge spikes a Leading Edge Blanking is

integrated in the current sense path for the

comparators C10, C12 and the PWM-OP.

The output of comparator C12 is activated by the Gate

G10 if Active Burst Mode is entered. Once activated the

current limiting is thereby reduced to 0.257V. This

voltage level determines the power level when the

Active Burst Mode is left if there is a higher power

demand.

A further comparator C11 is implemented to detect

dangerous current levels which could occur if there is a

3.5.2 Propagation Delay Compensation

In case of overcurrent detection, the switch-off of the

internal CoolMOSâ¢ is delayed due to the propagation

delay of the circuit. This delay causes an overshoot of

the peak current Ipeak which depends on the ratio of dI/

dt of the peak current (see Figure 11).

ISense

Ipeak2

Ipeak1

ILimit

Signal2

IOvershoot2

Signal1

tPropagation Delay

IOvershoot1

t

Figure 11 Current Limiting

The overshoot of Signal2 is bigger than of Signal1 due

to the steeper rising waveform. This change in the

slope is depending on the AC input voltage.

Propagation Delay Compensation is integrated to limit

the overshoot dependency on dI/dt of the rising primary

Version 2.0

10

8 May 2006

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