HYS64V32300GU Datasheet, PDF (10/16 Pages) Infineon Technologies AG – 3.3 V 32M x 64/72-Bit, 256MByte SDRAM Modules 168-pin Unbuffered DIMM Modules

HYS 64/72V32300GU
SDRAM-Modules
SPD-Table for 32M x 64 (256MByte non-ECC) Modules HYS64V32300GU
Byte# Description
0
Number of SPD Bytes
1
Total Bytes in Serial PD
2
Memory Type
3
Number of Row Addresses
4
Number of Column Addresses
5
Number of DIMM Banks
6
Module Data Width
7
Module Data Width (cont’d)
8
Module Interface Levels
9
SDRAM Cycle Time at CL = 3
10
SDRAM Access Time at CL = 3
11
DIMM Config
12
Refresh Rate/Type
13
SDRAM Width, Primary
14
Error Checking SDRAM Data Width
15
Minimum Clock Delay for Back-to-
Back Random Column Address
16
Burst Length Supported
17
Number of SDRAM Banks
18
Supported CAS Latencies
19
CS Latencies
20
WE Latencies
21
SDRAM DIMM Module Attributes
22
SDRAM Device Attributes: General
23
SDRAM Cycle Time at CL = 2
24
SDRAM Access Time at CL = 2
25
SDRAM Cycle Time at CL = 1
26
SDRAM Access Time at CL = 1
27
Minimum Row Precharge Time
28
Min. Row to Row Active Delay t_RRD
29
Minimum RAS to CAS Delay t_RCD
30
Minimum RAS Pulse Width t_RAS
31
Module Bank Density (per bank)
32
SDRAM Input Setup Time
33
SDRAM Input Hold Time
34
SDRAM Data Input Hold Time
35
SDRAM Data Input Setup Time
SPD Entry Value
128
256
SDRAM
13
10
1
64
0
LVTTL
7.5 / 10 ns
5.4 / 6 ns
non-ECC
Self-Refresh,
7.8 µs
x8
na
t_CCD = 1 CLK
1, 2, 4 & 8
4
CL = 2 & 3
CS latency = 0
Write latency = 0
unbuffered
V_DD tol +/– 10%
7.5 / 10.0 ns
5.4 / 6.0 ns
not supported
not supported
15 / 20 ns
14 / 15 / 16 ns
15 / 20 ns
42 / 45 / 50 ns
256 MByte
1.5 / 2.0 ns
0.8 / 1.0 ns
1.5 / 2.0 ns
0.8 / 1.0 ns
Hex
32M x 64
-7
-7.5
-8
80
08
04
0D
0A
01
40
00
01
75
75
A0
54
54
60
00
82
08
00
01
0F
04
06
01
01
00
0E
75
A0
A0
54
60
60
00
FF
FF
00
FF
FF
0F
14
14
0E
0F
10
0F
14
14
2A
2D
32
40
15
15
20
08
08
10
15
15
20
08
08
10
INFINEON Technologies
10
9.01