IDT82P2284 Datasheet, PDF (99/384 Pages) Integrated Device Technology – Quad T1/E1/J1 Long Haul / Short Haul Transceiver

IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Table 72: Transmit Waveform Value For DS1 -15.0 dB LBO
UI 1
UI 2
UI 3
UI 4
Sample 1 0000000
0110101
0001111
0000011
Sample 2
0000000
0110011
0001101
0000010
Sample 3
0000000
0110000
0001100
0000010
Sample 4
0000001
0101101
0001011
0000010
Sample 5 0000100 0101010 0001010 0000010
Sample 6 0001000 0100111 0001001 0000001
Sample 7 0001110 0100100 0001000 0000001
Sample 8 0010100 0100001 0000111 0000001
Sample 9
0011011
0011110
0000110
0000001
Sample 10 0100010
0011100
0000110
0000001
Sample 11 0101010 0011010 0000101 0000001
Sample 12 0110000 0010111 0000101 0000001
Sample 13 0110101 0010101 0000100 0000001
Sample 14 0110111
0010100
0000100
0000000
Sample 15 0111000 0010010 0000011 0000000
Sample 16 0110111
0010000
0000011
0000000
The standard value of the SCAL[5:0] bits is ‘001000’. One step change of the value
results in 12.5% scaling up/down against the pulse amplitude.
Table 73: Transmit Waveform Value For DS1 -22.5 dB LBO
UI 1
UI 2
UI 3
UI 4
Sample 1
0000000
0101100
0011110
0001000
Sample 2
0000000
0101110
0011100
0000111
Sample 3
0000000
0110000
0011010
0000110
Sample 4
0000000
0110001
0011000
0000101
Sample 5
0000001
0110010
0010111
0000101
Sample 6
0000011
0110010
0010101 0000100
Sample 7
0000111
0110010 0010100 0000100
Sample 8
0001011
0110001
0010011
0000011
Sample 9
0001111
0110000 0010001 0000011
Sample 10 0010101 0101110 0010000 0000010
Sample 11
0011001
0101100
0001111
0000010
Sample 12 0011100 0101001 0001110 0000010
Sample 13 0100000 0100111 0001101 0000001
Sample 14 0100011 0100100 0001100 0000001
Sample 15 0100111 0100010 0001010 0000001
Sample 16 0101010 0100000 0001001 0000001
The standard value of the SCAL[5:0] bits is ‘000100’. One step change of this value
results in 25% scaling up/down against the pulse amplitude.
When more than one UI are used to compose the pulse template
and the pulse amplitude is not set properly, the overlap of two consecu-
tive pulses will make the pulse amplitude overflow (exceed the maxi-
mum limitation). This overflow is captured by the DAC_IS bit, and if
enabled by the DAC_IE bit, an interrupt will be reported by the INT pin.
Table 74: Related Bit / Register In Chapter 3.24
Bit
PULS[3:0]
UI[1:0]
SAMP[3:0]
RW
DONE
WDAT[6:0]
SCAL[5:0]
DAC_IS
DAC_IE
Register
Transmit Configuration 1
Transmit Configuration 3
Transmit Configuration 4
Transmit Configuration 2
Interrupt Status 1
Interrupt Enable Control 1
Address (Hex)
023, 123, 223, 323
025, 125, 225, 325
026, 126, 226, 326
024, 124, 224, 324
03B, 13B, 23B, 33B
034, 134, 234, 334
88
March 22, 2004