IDT82P2284 Datasheet, PDF (110/384 Pages) Integrated Device Technology – Quad T1/E1/J1 Long Haul / Short Haul Transceiver

IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
4.5 INDIRECT REGISTER ACCESS SCHEME
In Receive CAS/RBS Buffer, Receive Payload Control and Trans-
mit Payload Control blocks, per-channel/per-timeslot indirect register is
accessed by using an indirect register access scheme.
4.5.1 INDIRECT REGISTER READ ACCESS
The indirect register read access is as follows:
- Read the BUSY bit in the Access Status register to confirm the bit
is ‘0’;
- Write the Access Control register to initiate the read operation and
specify the indirect register address;
- Read the BUSY bit in the Access Status register again to confirm
the bit is ‘0’;
- Read the indirect register data from the Access Data register.
An indirect register access request is completed within 4 µs.
4.5.2 INDIRECT REGISTER WRITE ACCESS
The indirect register write access is as follows:
- Read the BUSY bit in the Access Status register to confirm the bit
is ‘0’;
- Write the Access Data register;
- Write the Access Control register to initiate the write operation and
specify the indirect register address.
An indirect register access request is completed within 4 µs.
Table 81: Related Bit / Register In Chapter 4
Bit
-
T1/J1
FM[1:0]
TEMODE
R_OFF
T_OFF
BUSY
RWN
ADDRESS[6:0]
D[7:0]
Register
Software Reset
Address (Hex)
004
T1/J1 Or E1 Mode
020, 120, 220, 320
Receive Configuration 0
Transmit Configuration 0
TPLC Access Status / RPLC Access Status / RCRB Access Status
TPLC Access Control / RPLC Access Control
/ RCRB Access Control
TPLC Access Data / RPLC Access Data / RCRB Access Data
028, 128, 228, 328
022, 122, 222, 322
0C8, 1C8, 2C8, 3C8 / 0CD, 1CD, 2CD, 3CD / 0D3, 1D3, 2D3, 3D3
0C9, 1C9, 2C9, 3C9 / 0CE, 1CE, 2CE, 3CE / 0D4, 1D4, 2D4, 3D4
0CA, 1CA, 2CA, 3CA / 0CF, 1CF, 2CF, 3CF / 0D5, 1D5, 2D5, 3D5
Operation
99
March 22, 2004