IDT70824S Datasheet, PDF (9/21 Pages) Integrated Device Technology – HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM™)

IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Reset (RST)
Setting RST LOW resets the control state of the SARAM. RST functions
asynchronously of SCLK (i.e. not registered). The default states after a
reset operation are displayed in the adjacent chart.
Register
Address
EOB Flags
Contents
0
Cleared to HIGH state
Buffer Flow Mode
BUFFER CHAINING
Start Address Buffer #1
0 (1)
End Address Buffer #1
4095 (4K)
Start Address Buffer #2⁽¹⁾
Cleared (set at invalid points)
End Address Buffer #2⁽¹⁾
Cleared (set at invalid points)
Registered State
SCE = VIH, SR/W = VIL
NOTE:
3099 tbl 15
1. Start address and End of address for Buffer #2 and the Flow Control for
both Buffer #1 and #2, must be programmed as described in the "Buffer
Command Mode" section.
Buffer Command Mode (CMD)
Buffer Command Mode (CMD) allows the random access port to
control the state of the two buffers. Address pins A0-A2 and I/O pins I/O0-
I/O11 are used to access the start of buffer and the end of buffer addresses
and to set the flow control mode of each buffer. The Buffer Command Mode
also allows reading and clearing the status of the EOB flags. Seven different
CMD cases are available depending on the conditions of A0-A2 and R/
W. Address bits A3-A11and data I/O bits I/O12-I/O15are not used during
this operation.
Random Access Port CMD Mode⁽¹⁾
Case #
A2-A0
R/W
DESCRIPTIONS
1
000
0 (1) Write (read) the start address of Buffer #1 through I/O0-I/O11.
2
001
0 (1) Write (read) the end address of Buffer #1 through I/O0-I/O11.
3
010
0 (1) Write (read) the start address of Buffer #2 through I/O0-I/O11.
4
011
0 (1) Write (read) the end address of Buffer #2 through I/O0-I/O11.
5
100
0 (1) Write (read) flow control register.
6
101
0
Write only - clear EOB1 and/or EOB2 flag.
7
101
1
Read only - flag status register.
8
110/111
(X) (Reserved)
NOTE:
1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
3099 tbl 16
Cases 1 through 4: Start and End of Buffer Register Description^(1,2)
15 14 13 12 11 -------------------------------------------------------------------------------------------------- 0
MSB H H H L
Address Loaded into Buffer
LSB I/O BITS
NOTES:
3099 drw 10
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state. "L" = VIL for I/O in the input state.
2. A write into the buffer occurs when R/W = VIL and a read when R/W = VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD = VIL and
CE = VIH.
Case 5: Buffer Flow Modes
Within the SARAM, the user can designate one of two buffer flow modes
for each buffer. Each buffer flow mode defines a unique set of actions for
the sequential port address pointer and EOB flags. In BUFFER CHAIN-
ING mode, after the address pointer reaches the end of the buffer, it sets
the corresponding EOB flag and continues from the start address of the
other buffer. In STOP mode, the address pointer stops incrementing after
it reaches the end of the buffer. There is no linear or mask mode available.
6.942