IDT70824S Datasheet, PDF (5/21 Pages) Integrated Device Technology – HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM™)

IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range^(1,2,8) (VCC = 5.0V ± 10%)
70824X20
Com'l Only
70824X25
Com'l Only
70824X35
Com'l &
Military
70824X45
Com'l &
Military
Symbol
Parameter
Test Condition
Version
Typ.⁽²⁾ Max. Typ.⁽²⁾ Max. Typ.⁽²⁾ Max. Typ.⁽²⁾ Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CEL and CER = VIL,
Outputs Open
SCE = VIL⁽⁵⁾
f = fMAX⁽³⁾
COM'L
MIL &
IND
S 180 380 170 360 160 340 155 340 mA
L 180 330 170 310 160 290 155 290
S
____
____
____
____
160 400 155 400
L
____
____
____
____
160 340 155 340
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
SCE and CE = VIH⁽⁷⁾
CMD = VIH
f = fMAX⁽³⁾
COM'L
S 25
70
25
70
20
70
16
70 mA
L 25
50
25
50
20
50
16
50
MIL &
IND
S
____
____
____
____
20
85
16
85
L
____
____
____
____
20
65
16
65
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE or SCE = VIH
Active Port Outputs Open,
f=fMAX⁽³⁾
COM'L
S 115 260 105 250
95
240
90
240 mA
L 115 230 105 220
95
210
90
210
MIL &
IND
S
____
____
____
____
95
290
90
290
L
____
____
____
____
95
250
90
250
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE and
SCE > VCC - 0.2V⁽⁶⁾
VIN > VCC - 0.2V or
VIN < 0.^2V,
f = 0⁽⁴⁾
COM'L
S 1.0
15
1.0
15
1.0
15
1.0
15 mA
L 0.2
5
0.2
5
0.2
5
0.2
5
MIL &
IND
S
____
____
____
____
1.0
30
1.0
30
L
____
____
____
____
0.2
10
0.2
10
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE or
SCE > VCC - 0.2V^(6,7)
Outputs Open (Active Port)
f = fMAX⁽³⁾
VIN > VCC - 0.2V or VIN < 0.2V
COM'L
S 110 240 100 230
90
220
85
220 mA
L 110 200 100 190
90
180
85
180
MIL &
IND
S
____
____
____
____
90
260
85
260
L
____
____
____
____
90
215
85
215
NOTES
3099 tbl 08
1. 'X' in part number indicates power rating (S or L).
2. VCC = 5V, TA = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK.
6. SCE may be - 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = LOW) then the other port is disabled (SCE or CE = HIGH, respectively). CMOS HIGH > Vcc - 0.2V and LOW < 0.2V, and
TTL HIGH = VIH and LOW = VIL.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol
Parameter
Test Condition
Min.
Typ.⁽¹⁾
VDR
VCC for Data Retention
VCC = 2V
2.0
___
ICCDR
Data Retention Current
CE = VHC
MIL. & IND.
___
100
VIN = VHC or = VLC
COM'L.
___
100
tCDR⁽³⁾
Chip Deselect to Data Retention Time
SCE = VHC⁽⁴⁾ when SCLK = u
___
___
tR⁽³⁾
Operation Recovery Time
CMD > VHC
tRC⁽²⁾
___
NOTES :
1. TA = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
Max. Unit
___
V
4000
µA
1500
___
V
___
V
3099 tbl 09
6.542