IDT70824S Datasheet, PDF (1/21 Pages) Integrated Device Technology – HIGH-SPEED 4K X 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM™)

HIGH SPEED 64K (4K X 16 BIT)
IDT70824S/L
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM^™)
Features
x _{High-speed access}
– Military: 35/45ns (max.)
– Commercial: 20/25/35/45ns (max.)
x _{Low-power operation}
– IDT70824S
Active: 775mW (typ.)
Standby: 5mW (typ.)
– IDT70824L
Active: 775mW (typ.)
Standby: 1mW (typ.)
x _{4Kx16SequentialAccessRandomAccessMemory (SARAM}™₎
– Sequential Access from one port and standard Random
Access from the other port
– Separate upper-byte and lower-byte control of the
Random Access Port
x _{High speed operation}
– 20ns tAA for random access port
– 20ns tCD for sequential port
– 25ns clock cycle time
x _{Architecture based on Dual-Port RAM cells}
x _{Compatible with Intel BMIC and 82430 PCI Set}
x _{Width and Depth Expandable}
x _{Sequential side}
– Address based flags for buffer control
– Pointer logic supports up to two internal buffers
x _{Battery backup operation - 2V data retention}
x _{TTL-compatible, single 5V (+10%) power supply}
x _{Available in 80-pin TQFP and 84-pin PGA}
x _{Military product compliant to MIL-PRF-38535 QML}
x _{Industrial temperature range (–40°C to +85°C) is available}
for selected speeds
Description
The IDT70824 is a high-speed 4K x 16-Bit Sequential Access Random
Access Memory (SARAM). The SARAM offers a single-chip solution to
buffer data sequentially on one port, and be accessed randomly (asyn-
chronously) through the other port. The device has a Dual-Port RAM
based architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with counter se-
Functional Block Diagram
A0-11 ¹²
CE
OE
R/W
LB ^LSB
UB ^MSB
CMD
Random
Access
Port
Controls
I/O0-15
16
12
12
12
DataL
4K X 16
Memory
Array
DataR
AddrL
AddrR
12
12
Sequential
Access
Port
Controls
16
16
Reg.
12
RST
Pointer/
Counter
RST
SCLK
CNTEN
SOE
SSTRT1
SSTRT2
SCE
SR/W
SLD
SI/O0-15
,
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
12
End Address for Buffer #2
Flow Control Buffer
Flag Status
©2000 Integrated Device Technology, Inc.
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APRIL 2000
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