ICS8741004 Datasheet, PDF (9/17 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS8741004 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V_DD, V_DDA and V_DDO should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10µF and a 0.01µF
bypass capacitor should be connected to each V_DDA pin.
3.3V
V_DD
.01µF _10Ω
V_DDA
.01µF
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V_DD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
V_DD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
9
ICS8741004AG REV. AAUGUST 3, 2007