ICS8741004 Datasheet, PDF (3/17 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
1, 24
3, 22
4, 5
6
7
8
9
10
11
12
13
14
15, 16
Name
QA1, QA1
V_DDO
QA0, QA0
MR
BW_SEL
nc
V_DDA
F_SELA
V_DD
OEA
CLK
CLK
GND
Type
Output
Power
Output
Input Pulldown
Input
Unused
Power
Pullup/
Pulldown
Input Pulldown
Power
Input
Pullup
Input
Input
Power
Pulldown
Pullup
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs
Q[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B.
No connect.
Analog supply pin.
Frequency select pins for QAx/QAx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
Core supply pin.
Output enable for QAx pins. When HIGH, QAx/QAx outputs are enabled.
When LOW, the QAx/QAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Output enable for QBx pins. When HIGH, QBx/QBx outputs are enabled.
17
OEB
Input
Pullup _{When LOW, the QBx/QBx outputs are in a high impedance state.}
LVCMOS/LVTTL interface levels. See Table 3A.
18
19
20, 21
23, 24
F_SELB
IREF
QB0, QB0
QB1, QB1
Input
Input
Output
Output
Pulldown
Frequency select pins for QBx/QBx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
A fixed precision resistor (RREF = 475Ω) from this pin to ground provides a
reference current used for differential current-mode QB0/nQB0 clock outputs.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input Capacitance
R_PULLUP
Input Pullup Resistor
R_PULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
3
ICS8741004AG REV. AAUGUST 3, 2007