ICS8741004 Datasheet, PDF (10/17 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Differential Clock Input Interface
The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the V_PP and
V_CMR input requirements. Figures 3A to 3D show interface
examples for the HiPerClockS CLK/CLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
3.3V
R1
R2
50
50
CLK
nCLK
HiPerClockS
Input
Figure 3A. HiPerClockS CLK/CLK Input Driven by an
IDT HiPerClockS LVHSTL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50
50
nCLK
HiPerClockS
Input
R2
50
Figure 3B. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVPECL Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
CLK
nCLK
HiPerClockS
R1
R2
84
84
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
Receiver
Figure 3C. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/CLK Input Driven by
a 3.3V LVDS Driver
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
10
ICS8741004AG REV. AAUGUST 3, 2007