ICS874005-04 Datasheet, PDF (9/13 Pages) Integrated Device Technology – PCI EXPRESS™ JITTER ATTENUATOR

ICS874005-04
PCI EXPRESS™ JITTER ATTENUATOR
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS output buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
3. 3V
LVDS_Driv er
3. 3V
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS874005-04 application
schematic. In this example, the device is operated at V = 3.3V.
DD
The decoupling capacitor should be located as close as possible
to the power pin. The input is driven by a 3.3V LVPECL driver.
VDD = 3.3V
VDDO = 3.3V
R1
10 C3
10uF
C4
0. 01u
U1
1
2 ^nQB2
3
4
nQA1
QA1
MR
BW_SEL
F_SELA
OEA
5
6
7
8
9
10
11
12
VDD O
QA0
nQAO
MR
BW_SEL
VDD A
F_SELA
VDD
OEA
8740_I0_C5_S_₈₇ts₄₀s₀o₅p_-02₄4
Zo = 50 Ohm
Zo = 50 Ohm
QB2
24
23
VDDO
QB1
22
21
nQB1
QB0
nQB0
F_SELB
20
19
18
17
OEB
GND
GND
16
15
14
nC LK
C LK
13
F_SELB
OEB
nCLK
C LK
Zo = 50 Ohm
Zo = 50 Ohm
+
R2
100
-
Zo = 50 Ohm
Zo = 50 Ohm
+
R3
100
-
LVPECL Driv er
(U1:11)
(U1:4) (U1:23)
C5
C6
10uf .1uf
C7
C8
.1uf
.1uf
R4
R5
50
50
R6
50
FIGURE 5. ICS874005-04 SCHEMATIC EXAMPLE
IDT^™ / ICS^™ PCI EXPRESS™ JITTER ATTENUATOR
9
ICS874005AG-04 REV. A JULY 29, 2008