ICS874005-04 Datasheet, PDF (4/13 Pages) Integrated Device Technology – PCI EXPRESS™ JITTER ATTENUATOR

ICS874005-04
PCI EXPRESS™ JITTER ATTENUATOR
TABLE
4C.
DIFFERENTIAL
DC
CHARACTERISTICS,
V=
DD
V
DDO
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK
I_IH
Input High Current
nCLK
CLK
I_IL
Input Low Current
nCLK
V_PP
Peak-to-Peak Input Voltage; NOTE 1
V_CMR
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: V_IL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V_IH.
V = V = 3.465V
DD
IN
V = V = 3.465V
DD
IN
V_DD = V_IN = 3.465V
V_DD = V_IN = 3.465V
-5
-150
0.15
GND + 0.5
150
µA
5
µA
µA
µA
1.3
V
V_DD - 0.85 V
TABLE
4D.
LVDS
DC
CHARACTERISTICS,
V=
DD
V
DDO
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum
V_OD
Δ V_OD
V_OS
Δ V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
247
1.125
Typical
1.25
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
TABLE 5. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
tjit(θ)
tjit(cc)
Output Frequency
98
320
MHz
RMS Phase Jitter (Random);
NOTE 1
100MHz, Integration Range:
(1.875MHz – 20MHz)
0.88
ps
Cycle-to-Cycle Jitter, NOTE 2
QA, QB = ÷4
QA = ÷5
35
ps
75
ps
tsk(o)
Output Skew; NOTE 3
90
ps
tsk(b)
QAx
Bank Skew: NOTE 4
QBx
15
ps
68
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
48
500
ps
52
%
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and frequency, and with equal load conditions.
Measured at the differential cross points.
NOTE 4: Defined as skew within a bank of outputs at the same supply voltage and frequency, and with equal load
conditions.
IDT^™ / ICS^™ PCI EXPRESS™ JITTER ATTENUATOR
4
ICS874005AG-04 REV. A JULY 29, 2008