ICS874005-04 Datasheet, PDF (1/13 Pages) Integrated Device Technology – PCI EXPRESS™ JITTER ATTENUATOR

PCI EXPRESS™ JITTER ATTENUATOR
ICS874005-04
GENERAL DESCRIPTION
The ICS874005-04 is a high performance Diff-
ICS
erential-to-LVDS Jitter Attenuator designed for use
HiPerClockS™ _{in PCI Express systems. In some PCI Express}
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The
ICS874005-04 has 2 PLL bandwidth modes: 300kHz and
2MHz. The 300kHz mode will provide maximum jitter
attenuation, but higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. The 2MHz bandwidth provides the best tracking
skew and will pass most spread profiles. The ICS874005-04
supports Serdes reference clock frequencies of 100MHz,
125MHz and 250MHz.
The ICS874005-04 uses IDT’s 3^rd Generation FemtoClock^TM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
BLOCK DIAGRAM
OEA ^Pullup
F_SELA ^Pulldown
BW_SEL ^Pulldown
0 = ~300kHz
1 = ~2MHz
CLK ^Pulldown
nCLK ^Pullup
Phase
Detector
VCO
490 - 640MHz
M = ÷5 (fixed)
F_SELA
0 ÷5 (default)
1 ÷4
F_SELB
0 ÷2 (default)
1 ÷4
F_SELB ^Pulldown
MR ^Pulldown
OEB ^Pullup
FEATURES
• Five differential LVDS output pairs
• One differential clock input
• Supports 100MHz, 125MHz, and 250MHz Serdes reference
clocks
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 320MHz
• Input frequency range: 98MHz - 128MHz
• PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant
• RMS phase jitter @ 100MHz (1.875MHz – 20MHz):
0.88ps (typical)
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4
• 3.3V operating supply
• Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
PLL BANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~300kHz (default)
1 = PLL Bandwidth: ~2MHz
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
QB2
nQB2
PIN ASSIGNMENT
nQB2 1
nQA1 2
QA1 3
VDDO 4
QA0 5
nQA0 ⁶
MR ⁷
BW_SEL 8
VDDA ⁹
F_SELA ¹⁰
VDD ¹¹
OEA ¹²
24 QB2
23 VDDO
22 QB1
21 nQB1
20 QB0
19 nQB0
18 F_SELB
17 OEB
16 _GND
15 _GND
14 _nCLK
13 _CLK
ICS874005-04
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm package body
G Package
Top View
IDT^™ / ICS^™ PCI EXPRESS™ JITTER ATTENUATOR
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ICS874005AG-04 REV. A JULY 29, 2008