ICS853S54I Datasheet, PDF (9/21 Pages) Integrated Device Technology – Maximum output frequency

ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
LVPECL Clock Input Interface (2.5V)
The PCLK /nPCLK accepts LVPECL, LVDS and other differential
signals. The differential signal must meet the V_PP and V_CMR input
requirements. Figures 2A to 2C show interface examples for the
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
LVDS
Zo = 50Ω
Zo = 50Ω
2.5V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
2. 5V
Zo = 50Ω
Zo = 50Ω
2.5V LVPECL Driv er
R6
R7
100Ω-180Ω 100Ω-180Ω
2.5V
R1
100Ω
C1
C2
R3
100Ω
PCLK
nPCLK
R2
100Ω
R4
100Ω
Figure 2A. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
2.5V
LVPECL
Zo = 50Ω
Zo = 50Ω
2.5V
R3
250Ω
R4
250Ω
2.5V
PCLK
R1
62.5Ω
R2
62.5Ω
nPCLK
LVPECL
Input
Figure 2C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
ICS853S54AKI REVISION A OCTOBER 30, 2012
9
©2012 Integrated Device Technology, Inc.