ICS853S54I Datasheet, PDF (8/21 Pages) Integrated Device Technology – Maximum output frequency

ICS853S54I Data Sheet
DUAL 2:1, 1:2 DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
LVPECL Differential Clock Input Interface (3.3V)
The PCLK /nPCLK accepts LVDS, LVPECL, and other differential
signals. Both V_SWING and V_OH must meet the V_PP and V_CMR input
requirements. Figures 2A to 2C show interface examples for the
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
Zo = 50Ω
LVDS
Zo = 50Ω
R5
100Ω
3.3V
C1
C2
R1
R2
1k
1k
PCLK
VBB
nPCLK
LVPECL
Input
C3
0.1µF
Figure 2A. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84Ω
84Ω
Input
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125 125
3.3V
PCLK
nPCLK
LVPECL
Input
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
PCLK
R1
R2
120
120
nPCLK
LVPECL
Input
Figure 2C. PCLK/nPCLK Input Driven by a 3.3V LVPECL
Driver with AC Couple
Figure 2D. PCLK/nPCLK Input Driven by an SSTL Driver
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
Zo = 50Ω
CML Built-In Pullup
Zo = 50Ω
R1
100Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 2E. PCLK/nPCLK Input Driven by a CML Driver
Figure 2F. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
ICS853S54AKI REVISION A OCTOBER 30, 2012
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©2012 Integrated Device Technology, Inc.