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ICS853S057I Datasheet, PDF (9/16 Pages) Integrated Device Technology – Maximum input/output frequency | |||
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ICS853S057I Data Sheet
4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50â¦
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
3.3V
Zo = 50â¦
3.3V
+
LVPECL
Zo = 50â¦
R1
50â¦
RTT =
1
((VOH + VOL) / (VCC â 2)) â 2
* Zo
_
Input
R2
50â¦
VCC - 2V
RTT
Figure 3A. 3.3V LVPECL Output Termination
3.3V
LVPECL
3.3V
R3
R4
125â¦
125â¦
3.3V
Zo = 50â¦
+
Zo = 50â¦
R1
84â¦
_
R2
84â¦
Input
Figure 3B. 3.3V LVPECL Output Termination
ICS853S057AGI REVISION A MAY 16, 2012
9
©2012 Integrated Device Technology, Inc.
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