ICS853S057I Datasheet, PDF (1/16 Pages) Integrated Device Technology – Maximum input/output frequency

4:1, Differential-To-3.3V, 2.5V LVPECL/ECL
Clock Data Multiplexer
ICS853S057I
DATA SHEET
General Description
The ICS853S057I is a 4:1 Differential-to-3.3V or 2.5V LVPECL/ECL
Clock/Data Multiplexer which can operate up to 3GHz. The
ICS853S057I has 4 differential selectable clock input pairs. The
CLK, nCLK input pairs can accept LVPECL, LVDS, CML or SSTL
levels. The fully differential architecture and low propagation delay
make it ideal for use in clock distribution circuits. The multiplexer
select control inputs have ECL/LVPECL interface levels. The select
pins have internal pulldown resistors.
Features
• High speed 4:1 differential muliplexer
• One differential 3.3V, 2.5V LVPECL/ECL output
• Four differential CLKx, nCLKx input pairs
• Differential CLKx, nCLKx pairs can accept the following interface
levels: LVPECL, LVDS, CML, SSTL
• Maximum input/output frequency: 3GHz
• Additive phase jitter, RMS @ 622.08MHz: 0.073ps (typical)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 615ps (maximum)
• LVPECL mode operating voltage supply range:
V_CC = 2.375V to 3.465V, V_EE = 0V
• ECL mode operating voltage supply range:
V_CC = 0V, V_EE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
Block Diagram
CLK0 ^Pulldown
nCLK0 ^Pulldown
00
(default)
CLK1 ^Pulldown
nCLK1 ^Pulldown
01
Q
CLK2 ^Pulldown
nQ
nCLK2 ^Pulldown
10
CLK3 ^Pulldown
nCLK3 ^Pulldown
11
SEL1 ^Pulldown
SEL0 ^Pulldown
VBB1
V_BB2
Pin Assignment
VCC 1
CLK0 2
nCLK0 3
CLK1 4
nCLK1 5
CLK2 6
nCLK2 7
CLK3 8
nCLK3 9
VEE 10
20 VCC
19 SEL1
18 SEL0
17 VCC
16 Q
15 nQ
14 VCC
13 VBB1
12 VBB2
11 VEE
ICS853S057I
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS853S057AGI REVISION A MAY 16, 2012
1
©2012 Integrated Device Technology, Inc.