ICS853S057I Datasheet, PDF (8/16 Pages) Integrated Device Technology – Maximum input/output frequency

ICS853S057I Data Sheet
4:1, DIFFERENTIAL-TO-3.3V, 2.5V LVPECL/ECL CLOCK DATA MULTIPLEXER
Clock Input Interface
The CLK/nCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. Both V_SWING and V_OH must meet the V_PP and
V_CMR input requirements. Figures 2A to2E show interface examples
for the HiPerClockS CLK /nCLK input driven by the most common
driver types. The input interfaces suggested here are examples only.
If the driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the driver
component to confirm the driver termination requirements.
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50
50
3.3V
CLK
nCLK
Differential
Input
Figure 2A. HiPerClockS CLK/nCLK Input
Driven by a CML Driver
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
R4
125
125
3.3V
CLK
nCLK
Differential
R1
R2
84
84
Input
3.3V
CML Built-In Pullup
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
Differential
Input
Figure 2B. HiPerClockS CLK/nCLK Input
Driven by a Built-In Pullup CML Driver
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
100
nCLK
Differential
Input
Figure 2C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
R4
120
120
3.3V
CLK
R1
R2
120
120
nCLK
Differential
Input
Figure 2D. HiPerClockS CLK/nCLK Input Driven by
a 3.3V LVDS Driver
Figure 2E. HiPerClockS CLK/nCLK Input
Driven by an SSTL Driver
ICS853S057AGI REVISION A MAY 16, 2012
8
©2012 Integrated Device Technology, Inc.