ICS844201I-45 Datasheet, PDF (9/16 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Clock Generator

ICS844201I-45 Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS CLOCK GENERATOR
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (Z_T) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z₀) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 3A can be used
with either type of output structure. Figure 3B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS Termination
ICS844201BKI-45 MAY 27, 2017
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