ICS844201I-45 Datasheet, PDF (4/16 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Clock Generator

ICS844201I-45 Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS CLOCK GENERATOR
AC Electrical Characteristics
Table 5. AC Characteristics, V_DD = 3.3V ± 10%, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
f_OUT
tjit(Ø)
t_j
Output Frequency
RMS Phase Jitter,
Random; NOTE 1
Phase Jitter
Peak-to-Peak;
NOTE 2
t_{REFCLK_HF_RMS}
Phase Jitter RMS;
NOTE 3
t_{REFCLK_LF_RMS}
Phase Jitter RMS;
NOTE 3
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
125MHz, Integration Range:
12kHz – 20MHz
100MHz, Integration Range:
12kHz – 20MHz
125MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
125MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
125MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Low Band: 10kHz - 1.5MHz
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Low Band: 10kHz - 1.5MHz
20% to 80%
f_OUT = 125MHz
f_OUT = 100MHz
Minimum
250
48
46
Typical
125
100
0.773
0.792
12.51
13.48
1.13
1.25
0.32
0.33
Maximum
Units
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
450
ps
52
%
54
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized using a 25MHz crystal.
NOTE 1: Refer to Phase Noise Plots.
NOTE 2: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen
1 is 86ps peak-to-peak for a sample size of 10⁶ clock periods. See IDT Application Note PCI Express Reference Clock Requirements and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for t_{REFCLK_HF_RMS} (High
Band) and 3.0 ps RMS for t_{REFCLK_LF_RMS} (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the
PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
ICS844201BKI-45 MAY 27, 2017
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