ICS844201I-45 Datasheet, PDF (12/16 Pages) Integrated Device Technology – FemtoClock Crystal-to-LVDS Clock Generator

ICS844201I-45 Data Sheet
FEMTOCLOCK^® CRYSTAL-TO-LVDS CLOCK GENERATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844201I-45.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844201I-45 is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for V_DD = 3.3V + 10% = 3.63V, which gives worst case results.
• Power (core)_MAX = V_{DD_MAX} * I_{DD_MAX} = 3.63V * 95mA = 344.85mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.9°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.345W * 74.9°C/W = 110.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance _JA for 16 Lead VFQFN, Forced Convection
_JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
74.9°C/W
1
65.5°C/W
2.5
58.8°C/W
ICS844201BKI-45 MAY 27, 2017
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